Current demands for high density and performance associated with ultra large scale integration require submicron features of about 0.25 microns and under, increased transistor and circuit speeds and improved reliability. Such demands for increased density, performance and reliability require formation of device features with high precision and uniformity.
Conventional semiconductor devices comprise a substrate and various electrically isolated regions, called active regions, in which individual circuit components are formed. The electrical isolation of these active regions is typically accomplished by thermal oxidation of the semiconductor substrate, typically monocrystalline silicon or an epitaxial layer formed thereon, bounding the active regions.
One type of isolation structure is known as trench isolation, wherein shallow trenches are etched in the substrate and an oxide liner is thermally grown on the trench walls. The trench is then refilled with an insulating material. The resulting structure is referred to as a shallow trench isolation (STI) structure. The active region typically comprises source/drain regions formed in the semiconductor substrate by implantation of impurities, spaced apart by a channel region on which a gate electrode is formed with a gate oxide layer therebetween. The gate electrode controls the turn-on and turn-off of each transistor.
A typical method of trench formation comprises initially growing a pad oxide layer on the substrate, and depositing a nitride polish stop layer thereon. A photoresist mask is then applied to define the trench areas. The exposed portions of the nitride layer are then etched away, followed by the pad oxide layer. The etching continues into the substrate to form the shallow trench. When etching of the trench is completed, the photoresist is stripped off the nitride layer.
Next, the substrate is oxidized to form an oxide liner on the walls and base of the trench to control the silicon-silicon dioxide interface quality. The trench is then refilled with an insulating material (or "trench fill"), such as silicon dioxide derived from tetraethyl orthosilicate (TEOS). The surface is then planarized, as by chemical-mechanical polishing (CMP) using the nitride layer as a polish stop, and the nitride and pad oxide are stripped off the active areas to complete the trench isolation structure.
When creating the STI structure, it is considered ideal for the uppermost surface of the substrate to be flush (i.e., coplanar) with the uppermost surface of the trench fill, in order to provide a flat topography for subsequent processing, particularly photolithographic processing, thereby facilitating accurate formation of submicron features, particularly features of about 0.25 microns and under. However, substantial planarity is difficult to achieve. For example, the use of a nitride layer as a polish stop results in the undesirable formation of a step.
FIG. 1A illustrates the substrate 1, pad oxide layer 2, nitride polish stop layer 3, oxide liner 4 and insulating material 5. Planarization is implemented utilizing nitride layer 3 as a polish stop (FIG. 1B). The nitride layer 3 and pad oxide layer 2 are then stripped off (FIG. 1C), creating a step between the main surface 1a of substrate 1 and the uppermost surface 5a of the insulating material 5. The height of the step substantially corresponds to the combined thicknesses of the pad oxide layer R and the nitride polish stop layer S. The use of nitride polish stop layer 3 undesirably increases the height of the topographical step, adversely impacting planarity at the interface of substrate surface 1a and trench fill surface 5a. Such a topographical step renders it difficult to photolithographically process subsequent layers of the device with accuracy, particularly in forming submicron features, thereby adversely affecting process yield and production cost. This problem becomes more acute as circuit geometry is continuously reduced to the 0.25 micron and under regime.
Unfortunately, the thickness S of the nitride layer 3, typically about 1600 .ANG. to about 1800 .ANG., cannot be reduced to the minimum necessary for it to function effectively as a polish stop (typically between about 300 .ANG. and about 1000 .ANG. depending on variables in the polishing process), because its thickness is optimized for photolithographic processing in defining the source/drain mask which, in turn, defines the trench areas. Accurate photolithographic processing requires that the nitride layer 3 on which the mask is formed have a specific optical reflectivity which, in turn, requires the nitride layer 3 to have a thickness greater than that necessary for it to function as a polish stop. Furthermore, any change in the thickness of the nitride layer 3 must be made in quantum increments; e.g., 400 .ANG. either thicker or thinner at a time, because of the nature of its optical properties. It is therefore difficult to optimize the thickness S of the nitride layer 3 as to its polish stop function without adversely impacting subsequent photolithographic processing.
In copending application Ser. No. 08/993,859, filed Dec. 18, 1997 (Attorney Docket No. 1033-294), a method is disclosed for forming trench isolation wherein the thickness of the nitride polish stop layer is reduced vis-a-vis conventional practices, thereby reducing the topological step between the main surface of the semiconductor substrate and the uppermost surface of the trench fill. The disclosed methodology comprises forming, on the pad oxide layer, a nitride layer whose thickness is optimized for its function as a polish stop (i.e., between about 300 .ANG. and about 1000 .ANG.), then forming a reflectance compensation layer, such as silicon dioxide, on the nitride polish stop layer. The photoresist source/drain mask is formed on the reflectance compensation layer by a photolithographic process. The thickness of the reflectance compensation layer is such that the combined optical path length of the nitride polish stop layer and the reflectance compensation layer is about equal to the optical path length required by the photolithographic process, optical path length being the product of a material's index of refraction and its thickness. The trench is thereafter etched and filled with an insulating material, then the insulating material and the reflectance compensation layer are planarized, as by CMP.
With the provision of a reflectance compensation layer, the methodology disclosed in copending application Ser. No. 08/993,859 (Attorney Docket No. 1033-294) reduces the thickness of the nitride polish stop layer compared to conventional practices, thereby reducing the height of undesirable topological steps at the substrate/trench interface. However, this methodology is limited to reducing the step height only to the minimum thickness required for the nitride polish stop to perform its function; i.e., about 300 .ANG..
There exists a continuing need for a method of manufacturing a semiconductor device which enables further reduction in the topographical step between the uppermost surface of the substrate or epitaxial layer and the uppermost surface of the trench, without adversely affecting photolithographic processing of the source/drain mask.